This course will focus on the importance of addressing different security threats on modern hardware design, manufacturing, installation, and operating practices. In particular, the threats would be shown to be relevant at scales ranging from a single user to an entire nation's public infrastructure. Through theoretical analyses and relevant practical world case studies, the threats would be demonstrated, and then state-of-the-art defense techniques would be described. The course would borrow concepts from diverse fields of study such as cryptography, hardware design, circuit testing, algorithms, and machine learning.
INTENDED AUDIENCE: Post-graduate students, and final year undergraduate students
Debdeep Mukhopadhyay is currently a full Professor at the Department of Computer Science and Engineering, IIT-Kharagpur, India.At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Embedded Security and Side Channel Attacks( [ http://cse.iitkgp.ac.in/resgrp/seal/ | http://cse.iitkgp.ac.in/resgrp/seal/ ] ) . Prior to this he worked asAssociate Professor at IIT Kharagpur, visiting scientist at NTU Singapore, a visiting Associate Professor of NYU-Shanghai, Assistant Professor atIIT-Madras, and as Visiting Researcher at NYU Tandon-School-of-Engineering, USA. He holds a PhD, an MS, and a B. Tech from IIT Kharagpur, India.Dr. Mukhopadhyay’s research interests are Cryptography, Hardware Security, and VLSI. His books includeFault Tolerant Architectures for Cryptography and Hardware Security (Springer), Cryptography and Network Security (Mc Graw Hills),Hardware Security: Design, Threats, and Safeguards (CRC Press), and Timing Channels in Cryptography (Springer).He has written more than 150 papers in peer-reviewed conferences and journals and has collaborated with several Indian and Foreign Organizations.He has been in the program committee of several top International conferences and is an Associate Editor of the International Association of Cryptologic Research (IACR)Transactions of CHES, Journal of Hardware and Systems Security, Journal of Cryptographic Engineering, Springer. He has given several invited talks in industry and academia, including tutorial talks at premier conferences like CHES, WIFS, VLSID.Dr. Mukhopadhyay is the recipient of the prestigious Swarnajayanti DST Fellowship 2015-16, Young Scientist award from the Indian National Science Academy,the Young Engineer award from the Indian National Academy of Engineers, and is a Young Associate of the Indian Academy of Science. He was also awarded theOutstanding Young Faculty fellowship in 2011 from IIT Kharagpur, and the Techno-Inventor Best PhD award by the Indian Semiconductor Association.He has recently incubated a start-up on Hardware Security, ESP Pvt Ltd at IIT Kharagpur ( [ http://esp-research.com/ ).
COURSE LAYOUT:
Week 1 : Introduction, Finite Fields, AES Hardware, S-Box Week 2 : Algorithm to Hardware, Case Study on ECC, Intro to ECC Week 3 : Implementation of ECC, Hardware Design of ECC Week 4 : Introduction to Side Channel Analysis Week 5 : Advanced SCA, Introduction to Fault Attacks Week 6 : Advanced Fault Attacks, Algebraic Fault Analysis Week 7 : Countermeasures-I Week 8 : Countermeasures-II Week 9 : Introduction to PUFs, Designs on FPGAs, Machine Learning of PUFs Week 10 : Design-for-Testability for Cryptographic Designs Week 11 : Protocols, Challenges, Introduction to Micro-architectural attacks Week 12 : Advanced Micro-architectural attacks, Hardware monitoring for malwares using Hardware Performance Counters
SUGGESTED READING MATERIALS:
Debdeep Mukhopadhyay and Rajat Subhra Chakraborty, "Hardware Security: Design, Threats, and Safeguards", CRC PressRebeiro, Chester, Mukhopadhyay, Debdeep, Bhattacharya, Sarani,Timing Channels in CryptographyA Micro-Architectural PerspectivePatranabis Sikhar, Mukhopadhyay, Debdeep , Fault Tolerant Architectures for Cryptography and Hardware Security, SpringerReference Books:Ahmad-Reza Sadeghi and David Naccache (eds.): Towards Hardware-intrinsic Security: Theory and Practice, Springer.Ted Huffmire et al: Handbook of FPGA Design Security, Springer.Stefan Mangard, Elisabeth Oswald, Thomas Popp: Power analysis attacks - revealing the secrets of smart cards. Springer 2007.Doug Stinson, Cryptography Theory and Practice, CRC Press.
CERTIFICATION EXAM :
The exam is optional for a fee.
Date and Time of Exams: April 28 2019(Sunday). Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.
CERTIFICATION:
Final score will be calculated as : 25% assignment score + 75% final exam score
25% assignment score is calculated as 25% of average of Best 8 out of 12 assignments
E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Kharagpur.It will be e-verifiable at nptel.ac.in/noc.
