Multi-Core Computer Architecture – Storage and Interconnects

Dr. John Jose is an Assistant Professor in Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, Assam since July 2015. Prior to this he has over 10 years of teaching experience at both undergraduate and graduate level in AICTE approved NBA/NACC accredited engineering institutes in Kerala. He did his B.Tech degree in CSE from Cochin University, Kerala. He was a rank holder in M.Tech degree from Vellore Institute of Technology (VIT University). He completed his Ph.D degree from Indian Institute of Technology Madras. He is currently supervising 5 Ph.D thesis and 5 M.Tech thesis. His area of interests is in on-chip interconnection networks and cache management techniques for large multicore systems. Recently he has started working on pre-fetching and compression techniques for Tiled Chip Multicore Processors. He is the principal investigator of two sponsored R&D projects funded by DST, Govt of India. He is having active research collaboration with University of Catania-Italy, ITRI Taiwan, and BITS Pilani-Dubai Campus. During his doctoral studies in IIT Madras, he received outstanding teaching assistant award for eight consecutive semesters. He is a reviewer for many national and international peer reviewed journals and member of technical program committee for many IEEE/ACM national and international conferences. He is a resource person to computer architecture related symposia and workshops in many technical institutes all over India. He has given many technical presentations in various international conferences held at Brazil, UAE, Singapore, France, South Korea and United States in the fields of computer design, interconnection networks, and design automation. He has many international IEEE & ACM peer reviewed conference publications and few transactions journal papers to his credit. He is the recipient of ACM-SIGDA, IEEE-CEDA, IARCS & DRDO grants for various research presentations held in various international venues. He is the IIT Guwahati coordinator for Ishan Vikas program of MHRD, Govt. of India. He was the course coordinator and resource persons for MHRD sponsored GIAN course in Scalable On-Chip Interconnects for Many-Core Systems held in May 2017 at IIT Guwahati. He is a resource person for many career guidance seminars/ workshops to various technical institutes and schools. He is a motivational speaker for many companies, schools and engineering institutions. He is an active member of professional societies like ACM, IEEE, ISTE and CSI.

COURSE LAYOUT:

Week 1  :  Fundamentals of instruction pipeline for superscalar processor design
Week 2  :   Memory hierarchy design, cache memory - fundamentals and basic optimisations
Week 3  : Cache memory – advanced optimisations, performance improvement technqiues
Week 4  :  gem5 simulator – build and run, address translations using TLB and page table
Week 5  :  DRAM – organisation, access techniques, scheduling algorithms and signal systems.
Week 6  :  Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7  :  NoC router – architecture, design, routing algorithms and flow control techniques.
Week 8  :  Advanced topics in NoC and storage – compression, prefetching, QoS.

SUGGESTED READING MATERIALS:

1. Computer Architecture - A Quantitative Approach-5e John L. Hennessy, David A. Patterson Morgan Kaufman.
2. Memory System - Cache, DRAM and Disk Bruce Jacob, Spencer W. Ng, David T. Wang Morgan Kaufman.
3. Principles and Practices of Interconnection Networks William J. Dally, Brian P. Towles Elsevier.