Switching Circuits and Logic Design

Prof. IndranilSengupta has obtained his B.Tech.,M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of CSE, where he is presently a full Professor. He had been the former Heads of the Department of Computer Science and Engineering and also the School of Information Technology of the Institute. He has over 28 years of teaching and research experience. He has guided 22 PhD students, and has more than 200 publications to his credit in international journals and conferences. His research interests include reversible and quantum computing, VLSI design and testing, and information security.
He is a Senior Member of IEEE. He had been the General Chairs of Asian Test Symposium (ATS-2005), International Conference on Cryptology in India (INDOCRYPT-2008), International Symposium on VLSI Design and Test (VDAT-2012), International Symposium on Electronic System Design (ISED-2012), and the Conference on Reversible Computation (RC-2017). 


COURSE LAYOUT:

Week 1  :  Introduction to number systems and codes, error detection and correction, binary arithmetic.
Week 2  :   Switching primitives and logic gates, logic families: TTL, CMOS, memristors, all-optical realizations.
Week 3  : Boolean algebra: Boolean operations and functions, algebraic manipulation, minterms and maxterms, sum-of-products and product-of-sum representations, functional completeness.
Week 4  :  Minimization of Boolean functions: K-map method, prime implicants, don’t care conditions, Quine-McCluskey method, multi-level minimization.
Week 5  :  Design of combinational logic circuits: adders and subtractors, comparator, multiplexer, demultiplexer, encoder, etc.
Week 6  :  Representation of Boolean functions: binary decision diagram, Shannon’s decomposition, Reed-Muller canonical form, etc.
Week 7  :  Design of latches and flip-flops: SR, D, JK, T. Master-slave and edge-triggered flip-flops. Clocking and timing issues.
Week 8  :  Synthesis of synchronous sequential circuits, Mealy and Moore machines, state minimization.
Week 9  :  Design of registers, shift registers, ring counters, binary and BCD counters. General counter design methodology.
Week 10  :  Algorithmic state machine and data/control path design.
Week 11  :  Asynchronous sequential circuits: analysis and synthesis, minimization, static and dynamic hazards.
Week 12  :  Testing and fault diagnosis in digital circuits: fault modeling, test generation and fault simulation, fault diagnosis, design for testability and built-in self-test.

SUGGESTED READING MATERIALS:

1.ZviKohavi and Niraj K. Jha, “Switching and Finite Automata Theory”, 3rd Edition, Cambridge University Press, 2010.
2.M. Morris Mano and Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog HDL”, 5th Edition, Pearson Education, 2013. 
3.Randy H. Katz and Gaetano Borriello, “Contemporary Logic Design”, 2nd Edition, Pearson Education, 2005.