About the course
The course will introduce the participants to the basic design flow in VLSI physical design automation, the basic data structures and algorithms used for implementing the same. The course will also provide examples and assignments to help the participants to understand the concepts involved, and appreciate the main challenges therein.
Intended Audience
Computer Science and Engineering / Electronics and Communication Engineering / Electrical Engineering
Pre-requisites
Basic concepts in digital circuit design
Industries that will
recognize this course
Intel,
Cadence, Mentor Graphics, Synopsys, Xilinx
Course instructor
Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of Computer Science and Engineering, where he is presently a full Professor. He had been the former Heads of the Department of Computer Science and Engineering and also the School of Information Technology of the Institute. He has over 28 years of teaching and research experience. He has guided 22 PhD students, and has more than 200 publications to his credit in international journals and conferences. His research interests include cryptography and network security, VLSI design and testing, and mobile computing.
He is a Senior Member of IEEE. He had been the General Chairs of Asian Test Symposium (ATS-2005), International Conference on Cryptology in India (INDOCRYPT-2008), International Symposium on VLSI Design and Test (VDAT-2012), International Symposium on Electronic System Design (ISED-2012), and the upcoming Conference on reversible Computation (RC-2017). He had delivered invited and tutorial talks in several conferences in the areas of VLSI design and testing, and network security.
Course layout
Week 1 : Introduction to physical design automation
Week 2: Partitioning, Floorplanning and Placement
Week 3 : Grid Routing and Global Routing
Week 4 : Detailed Routing and Clock Design
Week 5 : Clock Routing and Power/Ground Routing
Week 6 : Static Timing Analysis and Timing Closure
Week 7 : Physical Synthesis and Performance Driven Design Flow
Week 8 : Interconnect Modeling and Layout Compaction
Week 9 : Introduction to Testing, Fault Modeling and Simulation
Week 10 : Test Pattern Generation, DFT and BIST
Week 11 : Low Power Design Techniques
Week 12 : Low Power Design Techniques (contd.)
Certification exam:
• The exam is optional for a fee. Exams will be on 23 April 2017.
• Time: Shift 1: 9am-12 noons; Shift 2: 2pm-5pm
• Any one shift can be chosen to write the exam for a course.
• Registration url: Announcements will be made when the registration form is open for registrations.
• The online registration form has
to be filled and the certification exam fee needs to be paid. More details will
be made available when the exam registration form is published.
Certificates:
• Final score will be calculated as : 25% assignment score + 75% final exam score.
• 25% assignment score is calculated as 25% of average of 12 weeks course: Best 8 out of 12 assignments.
• E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup. It will have the logos of NPTEL and IIT KHARAGPUR. It will be e-verifiable at nptel.ac.in/noc
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